000			03236cam a22003618i 4500
001			22948993
003			OSt
005			20260302174404.0
008			230131s2023 enk b 001 0 eng
010			_a 2023004179
020			_a9781009200813 (pbk.)
035			_a22948993
040			_aDLC _beng _erda _cJKRC _dDLC
082	0	0	_223 _a621.3815 _bSAU.S
100	1		_aSaurabh, Sneh. _eauthor _939668
245	1	0	_aIntroduction to VLSI design flow / _cby Sneh Saurabh.
250			_a1st.
260			_aCambridge, United Kingdom ; _aNew York, NY, USA : _bCambridge University Press, _c2023.
263			_a2304
300			_axxvi, 689 p. ; _c24 cm.
336			_atext _btxt _2rdacontent
337			_aunmediated _bn _2rdamedia
338			_avolume _bnc _2rdacarrier
365			_b950.00 _cRupees
504			_aIncludes bibliographical references and index.
520			_a"Chip designing is a complex task that requires an in-depth understanding of VLSI design flow, skills to employ sophisticated design tools, and keeping pace with the bleeding-edge semiconductor technologies. This lucid textbook is focused on fulfilling these requirements for students, as well as a refresher for professionals in the industry. The book consists of four parts. The first part describes foundational concepts related to VLSI design flow and integrated circuits. It also gives an overview of the design, verification, and test methods employed in a typical VLSI design flow. The second part of the book describes the logic implementation and verification steps such as simulation, static timing analysis, and formal methods. It also explains the modelling of hardware using Verilog and logic synthesis; technology libraries; and timing constraints along with logic, power, and timing optimization techniques. The third part of the book describes the design for test (DFT) methods for digital circuits. The fourth and final part describes physical design methods and physical verification. All the physical design implementation steps such as floorplanning, placement, clock-tree synthesis, and routing are described in this part. Moreover, physical verification steps, such as parasitic extraction, design rule checks (DRCs), electrical rule checks (ERCs), layout versus schematic (LVS) checks, and post-silicon validation are explained. Illustrations and pictorial representations are used liberally to simplify the explanation. Additionally, activities are suggested at the end of relevant chapters to help readers gain a practical understanding of VLSI design flow. Review questions and problems are given at the end of each chapter to revise the concepts. Recent trends and references are listed at the end of each chapter for further reading"-- _cProvided by publisher.
650		0	_aIntegrated circuits _xVery large scale integration. _933805
653			_aElectronics and Instrumentation Science
776	0	8	_iOnline version: _aSaurabh, Sneh. _tIntroduction to VLSI design flow _dCambridge, United Kingdom ; New York, NY, USA : Cambridge University Press, 2023 _z9781009200790 _w(DLC) 2023004180
906			_a7 _bcbc _corignew _d1 _eecip _f20 _gy-gencatlg
942			_2ddc _c1 _e23 _n0
999			_c613983 _d613983