03347cam a22003618i 450000100090000000300040000900500170001300800410003001000170007102000250008803500130011304000290012608200240015510000340017924500570021325000090027026000890027926300090036830000270037733600260040433700280043033800270045836500190048550400510050452018920055565000620244765300440250977601850255390600450273894200180278399900190280195201650282022948993OSt20260302174404.0230131s2023    enk      b    001 0 eng    a  2023004179  a9781009200813 (pbk.)  a22948993  aDLCbengerdacJKRCdDLC00223a621.3815bSAU.S1 aSaurabh, Sneh.eauthor93966810aIntroduction to VLSI design flow /cby Sneh Saurabh.  a1st.  aCambridge, United Kingdom ;aNew York, NY, USA :bCambridge University Press,c2023.  a2304  axxvi, 689 p. ;c24 cm.  atextbtxt2rdacontent  aunmediatedbn2rdamedia  avolumebnc2rdacarrier  b950.00cRupees  aIncludes bibliographical references and index.  a"Chip designing is a complex task that requires an in-depth understanding of VLSI design flow, skills to employ sophisticated design tools, and keeping pace with the bleeding-edge semiconductor technologies. This lucid textbook is focused on fulfilling these requirements for students, as well as a refresher for professionals in the industry. The book consists of four parts. The first part describes foundational concepts related to VLSI design flow and integrated circuits. It also gives an overview of the design, verification, and test methods employed in a typical VLSI design flow. The second part of the book describes the logic implementation and verification steps such as simulation, static timing analysis, and formal methods. It also explains the modelling of hardware using Verilog and logic synthesis; technology libraries; and timing constraints along with logic, power, and timing optimization techniques. The third part of the book describes the design for test (DFT) methods for digital circuits. The fourth and final part describes physical design methods and physical verification. All the physical design implementation steps such as floorplanning, placement, clock-tree synthesis, and routing are described in this part. Moreover, physical verification steps, such as parasitic extraction, design rule checks (DRCs), electrical rule checks (ERCs), layout versus schematic (LVS) checks, and post-silicon validation are explained. Illustrations and pictorial representations are used liberally to simplify the explanation. Additionally, activities are suggested at the end of relevant chapters to help readers gain a practical understanding of VLSI design flow. Review questions and problems are given at the end of each chapter to revise the concepts. Recent trends and references are listed at the end of each chapter for further reading"--cProvided by publisher. 0aIntegrated circuitsxVery large scale integration.933805  aElectronics and Instrumentation Science08iOnline version:aSaurabh, Sneh.tIntroduction to VLSI design flowdCambridge, United Kingdom ; New York, NY, USA : Cambridge University Press, 2023z9781009200790w(DLC) 2023004180  a7bcbccorignewd1eecipf20gy-gencatlg  2ddcc1e23n0  c613983d613983  00102ddc4070a2b2d2026-03-02eUniversal Book Service, 234 / 05-01-2026i523857l0o621.3815 SAU.Sp523857r2026-03-02v950.00w2026-03-02y1z950.00 Rupees