MARC details
| 000 -LEADER |
|---|
| fixed length control field |
03236cam a22003618i 4500 |
| 001 - CONTROL NUMBER |
|---|
| control field |
22948993 |
| 003 - CONTROL NUMBER IDENTIFIER |
|---|
| control field |
OSt |
| 005 - DATE AND TIME OF LATEST TRANSACTION |
|---|
| control field |
20260302174404.0 |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION |
|---|
| fixed length control field |
230131s2023 enk b 001 0 eng |
| 010 ## - LIBRARY OF CONGRESS CONTROL NUMBER |
|---|
| LC control number |
2023004179 |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER |
|---|
| International Standard Book Number |
9781009200813 (pbk.) |
| 035 ## - SYSTEM CONTROL NUMBER |
|---|
| System control number |
22948993 |
| 040 ## - CATALOGING SOURCE |
|---|
| Original cataloging agency |
DLC |
| Language of cataloging |
eng |
| Description conventions |
rda |
| Transcribing agency |
JKRC |
| Modifying agency |
DLC |
| 082 00 - DEWEY DECIMAL CLASSIFICATION NUMBER |
|---|
| Edition number |
23 |
| Classification number |
621.3815 |
| Item number |
SAU.S |
| 100 1# - MAIN ENTRY--PERSONAL NAME |
|---|
| Personal name |
Saurabh, Sneh. |
| Relator term |
author |
| 9 (RLIN) |
39668 |
| 245 10 - TITLE STATEMENT |
|---|
| Title |
Introduction to VLSI design flow / |
| Statement of responsibility, etc. |
by Sneh Saurabh. |
| 250 ## - EDITION STATEMENT |
|---|
| Edition statement |
1st. |
| 260 ## - PUBLICATION, DISTRIBUTION, ETC. |
|---|
| Place of publication, distribution, etc. |
Cambridge, United Kingdom ; |
| -- |
New York, NY, USA : |
| Name of publisher, distributor, etc. |
Cambridge University Press, |
| Date of publication, distribution, etc. |
2023. |
| 263 ## - PROJECTED PUBLICATION DATE |
|---|
| Projected publication date |
2304 |
| 300 ## - PHYSICAL DESCRIPTION |
|---|
| Extent |
xxvi, 689 p. ; |
| Dimensions |
24 cm. |
| 336 ## - CONTENT TYPE |
|---|
| Content type term |
text |
| Content type code |
txt |
| Source |
rdacontent |
| 337 ## - MEDIA TYPE |
|---|
| Media type term |
unmediated |
| Media type code |
n |
| Source |
rdamedia |
| 338 ## - CARRIER TYPE |
|---|
| Carrier type term |
volume |
| Carrier type code |
nc |
| Source |
rdacarrier |
| 365 ## - TRADE PRICE |
|---|
| Price amount |
950.00 |
| Currency code |
Rupees |
| 504 ## - BIBLIOGRAPHY, ETC. NOTE |
|---|
| Bibliography, etc. note |
Includes bibliographical references and index. |
| 520 ## - SUMMARY, ETC. |
|---|
| Summary, etc. |
"Chip designing is a complex task that requires an in-depth understanding of VLSI design flow, skills to employ sophisticated design tools, and keeping pace with the bleeding-edge semiconductor technologies. This lucid textbook is focused on fulfilling these requirements for students, as well as a refresher for professionals in the industry. The book consists of four parts. The first part describes foundational concepts related to VLSI design flow and integrated circuits. It also gives an overview of the design, verification, and test methods employed in a typical VLSI design flow. The second part of the book describes the logic implementation and verification steps such as simulation, static timing analysis, and formal methods. It also explains the modelling of hardware using Verilog and logic synthesis; technology libraries; and timing constraints along with logic, power, and timing optimization techniques. The third part of the book describes the design for test (DFT) methods for digital circuits. The fourth and final part describes physical design methods and physical verification. All the physical design implementation steps such as floorplanning, placement, clock-tree synthesis, and routing are described in this part. Moreover, physical verification steps, such as parasitic extraction, design rule checks (DRCs), electrical rule checks (ERCs), layout versus schematic (LVS) checks, and post-silicon validation are explained. Illustrations and pictorial representations are used liberally to simplify the explanation. Additionally, activities are suggested at the end of relevant chapters to help readers gain a practical understanding of VLSI design flow. Review questions and problems are given at the end of each chapter to revise the concepts. Recent trends and references are listed at the end of each chapter for further reading"-- |
| Assigning source |
Provided by publisher. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Topical term or geographic name entry element |
Integrated circuits |
| General subdivision |
Very large scale integration. |
| 9 (RLIN) |
33805 |
| 653 ## - INDEX TERM--UNCONTROLLED |
|---|
| Uncontrolled term |
Electronics and Instrumentation Science |
| 776 08 - ADDITIONAL PHYSICAL FORM ENTRY |
|---|
| Relationship information |
Online version: |
| Main entry heading |
Saurabh, Sneh. |
| Title |
Introduction to VLSI design flow |
| Place, publisher, and date of publication |
Cambridge, United Kingdom ; New York, NY, USA : Cambridge University Press, 2023 |
| International Standard Book Number |
9781009200790 |
| Record control number |
(DLC) 2023004180 |
| 906 ## - LOCAL DATA ELEMENT F, LDF (RLIN) |
|---|
| a |
7 |
| b |
cbc |
| c |
orignew |
| d |
1 |
| e |
ecip |
| f |
20 |
| g |
y-gencatlg |
| 942 ## - ADDED ENTRY ELEMENTS (KOHA) |
|---|
| Source of classification or shelving scheme |
|
| Koha item type |
Books |
| Edition |
23 |
| Suppress in OPAC |
No |